(1) Field of the Invention
The present invention relates to an address buffer circuit, more particularly to an address buffer circuit which is used in a memory device, for example, in an EPROM (Erasable and Programmable Read Only Memory), and which enables high speed testing of the memory device.
(2) Description of the Prior Art
In general, a semiconductor memory device such as an EPROM or RAM device is put to various operation tests before shipment from a factory. For example, the functions of reading-out and writing-in of test data are tested under various conditions. Such reading-out and writing-in tests are effected for all memory cells contained in the memory device.
However, since a conventional memory device can select only a word, consisting for example of one bit, at a time, the reading-out and writing-in tests are effected for only a single word at a time. Therefore, it takes a long time to test one memory device. Moreover, in recent years, the capacity of memory devices has become very large due to the increase in the degree of integration of the memory devices, and thus the abovementioned tests require a very long time. In particular in EPROM devices which have a relatively long writing-in time, the tests, which include a writing-in process, take a very long time.
An example of a prior art memory device is disclosed in the thesis "A 4K static Clocked and Nonclocked RAM Design," by Timothy R. O'Connel et al., the DIGEST OF TECHNICAL PAPERS In IEEE International Solid-State Circuits Conference, February 1977, PP 14-15.